1. Field of the Invention
The present invention relates to minimizing data retrieval time and/or area, or more particularly, to a system and method for minimizing read-only data retrieval time and/or area by using combinatorial logic to provide read-only data to a requester.
2. Description of Related Art
Electronic circuits typically operate in conjunction with at least one form of memory. For example, a personal computer generally includes a central processing unit (CPU) that operates in conjunction with random-access memory (RAM) and read-only memory (ROM)xe2x80x94the major difference being that RAM can both store and retrieve user defined data whereas ROM can only retrieve data established at the time of manufacture.
Typically, RAM is constructed by dividing a read/write portion of memory into discrete address bits, thus allowing data to be stored at, and retrieved from, a particular address location. For example, in response to a computer user providing a data-processing program (e.g., Word, Word Perfect, etc.) with the word xe2x80x9cdog,xe2x80x9d the program might temporarily store the word in RAM at a particular address location (e.g., address one-thousand). If the document is subsequently printed, the program will retrieve the word xe2x80x9cdogxe2x80x9d from the previously stored address location (e.g., address one-thousand) and provide it to the designated printer.
As well, ROM, regardless of its limited use (in that it cannot store user provided data), is typically constructed in the same fashion. A read-only portion of memory is divided into discrete address bits to allow read-only data to be retrieved from a particular address location. For example, a Pentium processor, which uses load constant instructions, may retrieve these constants from a particular address location in ROMxe2x80x94these constants being established at known addresses in the ROM module at the time of manufacturing.
The benefit of similar construction is that all forms of dataxe2x80x94both stored and manufacturer established (i.e., read-only) dataxe2x80x94can be retrieved by merely providing the memory module with the address location at which the data is located. The disadvantage of using such a similar construction is that both memory modules take roughly the same amount of time to execute (i.e., roughly an entire clock cycle), and utilize the same amount of real estate to store a single bit of data. In other words, ROM, which is more simplistic (in terms of read/write) than RAM, takes approximately the same amount of time to execute an instruction (i.e., provide data), and uses the same amount of area (per bit), as RAM.
This becomes especially problematic when the read-only memory (ROM) is small in comparison to the random-access memory (RAM), because a relatively large amount of time (usually an entire clock cycle) is needed to differentiate between a relatively small amount of manufacturer established data (i.e., the read-only data stored in ROM). Thus it would be desirable to have a system and method that minimizes read-only data retrieval time and/or area for ROM devices.
The present invention provides a system and method for minimizing read-only data retrieval time through the use of combinatorial logic. One embodiment of the present invention is directed to a two-bit address system. In this embodiment, two address bits are provided to a binary logic function device. The binary logic function device uses the two address bits and predetermined logic functions (i.e., functions that represent a plurality of read-only data values) to produce binary values. The resulting binary value is the read-only data requested.
Another embodiment of the present invention is directed to a three-bit address system. In this embodiment, two of the address bits are used as in the first embodiment, with the binary values (resulting from the binary logic function device) being provided to a multiplexer. The multiplexer uses the remaining address bit to select which binary value is the read-only data that has been requested.
Another embodiment of the present invention is directed to a multi-bit address systems (e.g., a six-bit address systems). In this embodiment, the binary values (resulting from the binary logic device) are provided to at least one multiplexer (the number of multiplexers and/or their ratios being determined by the number of address bits available as well as the characteristics of the miltiplexers available to the designer). The multiplexer uses a portion of the remaining bits (i.e., the address bits not being provided to the binary logic function device) to select (or narrow down) which binary value is the read-only data that has been requested. These narrowed down values are then provided to at least one other multiplexerxe2x80x94where the remainder of the remaining bits are used to select which value is the read-only data that has been requested.
A more complete understanding of the system and method for minimizing read-only data retrieval time by using combinatorial logic will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by a consideration of the following detailed description of the preferred embodiment. Reference will be made to the appended sheets of drawings which will first be described briefly.